In this work we introduce OpenVADL, a fully open-source implementation of the Vienna Architecture Description Language (VADL). From a single formal processor specification it generates an assembler, an LLVM-based compiler backend, a QEMU-based instruction-set simulator and even synthesizable hardware descriptions — cleanly separating ISA and micro-architecture layers in the process. The paper was published in the proceedings of the Architecture of Computing Systems (ARCS) 2025 conference. I highly encourage you to read the full paper for the design details and empirical evaluation demonstrating the toolchain’s capabilities.