Note: The SAMOS’25 online publication will appear in spring 2026.

In this work, we present the design and implementation of an automated generator that produces a fully functional QEMU frontend directly from a high-level processor specification written in the Vienna Architecture Description Language (VADL). The approach eliminates the need for manually implementing instruction set simulators and ensures consistency between architectural specification and simulation.

The generator translates the VADL-based intermediate representation into QEMU’s Tiny Code Generator (TCG) IR, including automated decode tree construction, instruction lowering, side-effect scheduling, and optimization for translation block chaining. The resulting simulator integrates seamlessly into the QEMU ecosystem, including support for features such as GDB debugging.

An evaluation using the Embench benchmark suite shows that the generated QEMU frontend achieves competitive performance and reaches up to 1.77× speedup compared to the handwritten upstream RISC-V RV64IM frontend.